Intel Unveils 3D CMOS Breakthrough Paving Moore's Law Future

At the annual IEEE International Electron Devices Meeting (IEDM) 2023, Intel showcased several important process technology advancements that will help extend Moore's Law and boost computing power in the coming years. Intel researchers demonstrated the industry's first vertically stacked complementary metal-oxide-semiconductor (CMOS) transistors with a scaled gate pitch of 60 nanometers. This 3D transistor integration allows for greater area efficiency and performance by stacking more transistors in the same footprint.

Intel's new 3D CMOS design is significantly combined with backside power delivery and direct backside contacts. According to Intel, this combination of technologies represents a major step forward that underscores its leadership in advanced transistor architectures like gate-all-around designs.

Sanjay Natarajan, Intel senior vice president and general manager of Components Research said, “As we enter the Angstrom Era and look beyond five nodes in four years, continued innovation is more critical than ever. At IEDM 2023, Intel showcases its progress with research advancements that fuel Moore’s Law, underscoring our ability to bring leading-edge technologies that enable further scaling and efficient power delivery for the next generation of mobile computing.”

In addition, Intel announced it has successfully fabricated the world's first large-scale integrated circuit that combines silicon transistors with gallium nitride (GaN) transistors on the same 300mm wafer. Codenamed "DrGaN", Intel said this mixed-material integration could potentially enable more efficient power delivery solutions needed by future high-performance processors.

Intel has also outlined key research areas crucial for continued transistor scaling using backside power delivery technologies. Its "PowerVia" implementation is on track to enter manufacturing in 2024. Researchers also highlighted the potential of two-dimensional transition metal dichalcogenide (TMD) channel materials to enable transistors with physical gate lengths under 10nm. Intel will also showcase the industry's first gate-all-around 2D TMD PMOS transistor fabricated on a 300mm wafer at IEDM 2023 later this week.